Note that your Top module should be the top logic module that you would like to synthesize. Similarly, your Top module can be set with: The Verilog source files are read with the command:Ĭlearly, changing the filename will change which file gets loaded into the compiler. You will have to read the documentations on your own if you really want to be good at this. Should you be motivated to modify the synthesis script, here is a quick run through. We do not suggest modifying the dc scripts beyond changing your top module and source files. The prized netlist should also be written to the current directory. Finally, it should begin mapping your Verilog description to the standard cell library and generate reports for area, power, and timing (output in area.rpt, power.rpt, and timing.rpt, respectively). If all goes well, the compiler should churn for a little time (or lots, depending on the complexity of your circuit).
Error messages, on the other hand, are definitely bad news. You should investigate them, although many such warning messages do not indicate a show-stopper problem with your Verilog. Depending on what you did, you should also expect to see a number of common warnings. After this, it will read your Verilog file and load the technology library (in this case, an 180nm standard cell library). You should see a startup banner for Design Compiler and it should briefly print “Initializing…”. In your working directory with both your Verilog code (e.g., lab0.v) and the synthesis script (e.g., lab0.dc), run the following command on any of ECE's Linux machines: (You can find and replace these specific names in lab0.dc when you want to reuse the script in a future lab.)
The FSM module must have a clock input port named clock and a reset input port named reset. These scripts are hard-coded to list which Verilog file(s) to compile, your top module for synthesis, and the name of your clock signal.įor lab0, to use /afs/ece/class/ece447/handout/lab0/lab0.dc, the module to be synthesized must be called FSM in a file called lab0.v. Design Compiler uses a special script file to setup and direct compilation of your Verilog description.
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